Recent Publications in Secure Hardware

Conference Presentations/Papers

  1. H. Kumar, N. Chawla, and S. Mukhopadhyay, “Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty Estimation,” Design Automation Conference, 2021.
  2. H. Kumar, N. Chawla, and S. Mukhopadhyay, “BiasP: A DVFS based Exploit to Undermine Resource Allocation Fairness in Linux Platforms,” IEEE/ACM International Symposium on Low-Power Electronic Design (ISLPED), August 2020.
  3. E. Lee, N. M. Rahman, V. Chekuri, and S. Mukhopadhyay, “An Authentication IC with Visible Light Based Interrogation in 65nm CMOS,” IEEE Custom Integrated Circuit Conference, March 2020.
  4. N. M. Rahman, E. Lee, V. Chekuri, A. Singh, and S. Mukhopadhyay, “A Configurable Dual-Mode PRINCE Cipher with Security Aware Pipelining in 65nm for High Throughput Applications,” IEEE Custom Integrated Circuit Conference, March 2020.
  5. N. Chawla, A. Singh, M. Kar,and S. Mukhopadhyay, “Application Inference using Machine Learning based Side Channel Analysis,” IEEE International Joint Conference on Neural Network (IJCNN), July 2019.
  6. N. Chawla, N. M. Rahman, A. Singh, M. Kar, and S. Mukhopadhyay, “Extracting side-channel leakage from round unrolled implementations of lightweight ciphers,” IEEE International Symposium on Hardware Oriented Security and Trust(HOST), May 2019.
  7. A. Singh, M. Kar, N. Chawla, and S. Mukhopadhyay, “Mitigating Power Supply Glitch based Fault Attacks with Fast All-Digital Clock Modulation Circuit,” Design Automation and Test in Europe(DATE), March 2019.
  8. A. Singh, M. Kar, S. Matthew, A. Rajan, V. De, and S. Mukhopadhyay, “A 128b AES Engine with Higher Resistance to Power and Electromagnetic Side-Channel Attacks Enabled by a Security-Aware Integrated All-Digital Low-Dropout Regulator,” IEEE International Solid State Circuit Conference (ISSCC), Feb 2019.
  9. A. Singh, N. Chawla, M. Kar, and S. Mukhopadhyay, “Energy Efficient and Side-Channel Secure Hardware Architecture for Lightweight Cipher SIMON,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
  10. (Invited) A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Exploiting On-Chip Power Management For Side-Channel Security,” Design, Automation, and Test in Europe (DATE), 2018.
  11. A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power Side Channel Attack Resistance of a 128-Bit AES Engine with Random Fast Voltage Dithering,” IEEE European Solid State Circuit Conference (ESSCIRC), 2017.
  12. (Invited) M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Low Power Requirements and Side-Channel Protection of Encryption Engines: Challenges and Opportunities,” International Symposium on Low-power Electronics and Design (ISLPED) 2017.
  13. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power Side-Channel Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator,” International Solid State Circuit Conference (ISSCC), 2017.
  14. M. Kar, A. Singh, A. Rajan, V. De, and S. Mukhopadhyay, “What does ultra low power requirements mean for side-channel secure cryptography?,” IEEE International Conference on Computer Design (ICCD), 2016.
  15. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De and S. Mukhopadhyay. “Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016.
  16. A. Singh, M. Kar, A. Rajan, V. De, and S. Mukhoapdhyay, “Integrated All-Digital Low-dropout Regulator as a Countermeasure to Power Attack in Encryption Engines,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016.
  17. A. Singh, M. Kar, and S. Mukhopadhyay, “Exploring Power Attack Protection of Resource Constrained Encryption Engines using Integrated Low-Drop-Out Regulators,” IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED), July 2015.
  18. M. Kar, A. Singh, D. Lie, M.Wolf, and S. Mukhopadhyay, “Improving Power Attack Immunity of Integrated Circuits using Integrated Inductive Voltage Regulators,” GOMACTECH, March 2015.
  19. M. Kar, D. Lie, M. Wolf, V. De, and S. Mukhopadhyay, “Impact of Inductive Integrated Voltage Regulator on the Power Attack Vulnerability of Encryption Engines: A Simulation Study,” IEEE Custom Integrated Circuit Conference (CICC), Sept. 2014.

Journal Articles

  1. E. Lee, N. Rahman, V. Chekuri, A. Singh and S. Mukhopadhyay, “A low power authentication IC for visible light based interrogation”, accepted for publication in IEEE Transactions on Industrial Electronics (TIE).
  2. N. Chawla, A. Singh, H. Kumar, M. Kar, and S. Mukhopadhyay, “Securing IoT Devices using Dynamic Power Management: Machine Learning Approach,” accepted for publication in IEEE Internet of Things Journal (IOT-J).
  3. A. Singh, M. Kar, V. Chekuri, S. Matthew, A. Rajan, V. De, and S. Mukhopadhyay, “Enhanced Power & Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO,” IEEE Journal of Solid State Circuits (JSSC), vol. 55, no. 2 , Feb. 2020, pp. 478 – 493.
  4. A. Singh, M. Kar, S. Matthew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power/EM Side Channel Attack Resistance of 128-bit AES Engines with Random Fast Voltage Dithering,” IEEE Journal of Solid State Circuits (JSSC), vol. 54, no. 2, Feb. 2019, pp. 569 – 583
  5. A. Singh, N. Chawla, J. H. Ko, M. Kar, and S. Mukhopadhyay,“Energy Efficient and Side-Channel Secure Cryptographic Hardware for IoT-edge Nodes,” IEEE Internet-of-Things Journal (IOT-J), vol 6, no. 1, Feb. 2019, pp. 421-434.
  6. N. Kumar, J. Chen, M. Kar, S. K. Sitaraman, S. Mukhopadhyay, and S. Kumar, “Multi-gated Carbon Nanotube Field Effect Transistors based Physically Unclonable Functions as Security Key,” IEEE Internet-of-Things Journal(IOT-J), vol 6, no. 1, Feb. 2019, pp. 325-334.
  7. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Reducing Power Side Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator,” IEEE Journal of Solid State Circuits (JSSC), vol 53, no. 8, August 2018, pp. 2399-2414.
  8. A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators,” Journal of Hardware and Systems Security, vol.1, December, 2017, pp. 340-355.