Recent Publications in Advanced 2.5D/3D Packaging

Journal Articles

  1. D. Kim, E. Lee, J. Seo, J. Kim, S. K. Lim, and S. Mukhopadhyay, “An SRAM Compiler for Monolithic-3D Integrated Circuit with Carbon Nanotube Transistors,” accepted for publications in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JXCDC).
  2. J. Kim, V. Chekuri, N. Rahman, M. Dolatsara, H. Torun, M. Swaminathan, S. Mukhopadhyay, and S. K. Lim, “Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5D ICs”, accepted for publication in IEEE Transactions on Components, Packaging and Manufacturing Technology.
  3. E. Lee, D. Kim, J. Kim, S. Lim and S. Mukhopadhyay, “A ReRAM Memory Compiler for Monolithic-3D Integrated Circuits in a Carbon Nanotube Process”, accepted for publication at ACM Journal on Emerging Technologies in Computing Systems(JETC).
  4. A. Chaudhuri, S. Banerjee, H. Park, J. Kim, G. Murali, E. Lee, D. Kim, S. K. Lim, S. Mukhopadhyay, and K. Chakrabarty, “Advances in Design and Test of Monolithic 3D ICs,” IEEE Design Test, 2020, vol. 37, no. 4, August 2020, pp. 92-100.
  5. J. Kim, G. Murali, H. Park, E. Qin, H. Kwon, V. Chekuri, N. M. Rahman, N. Dasari, A. Singh, M. Lee, H. M. Torun, K. Roy, M. Swaminathan, S. Mukhopadhyay, T. Krishna, and S. K. Lim, “Architecture, Chip, and Package Co-design Flow for Interposer-based 2.5D Chiplet Integration Enabling Heterogeneous IP Reuse,” IEEE Transactions on VLSI Systems (TVLSI), vol. 28, no 11, November 2020, pp. 2424-2437.
  6. H. Park, J. Kim, V. Chekuri, M. Dolatsara, M. Nabeel, A. Bojesomo, S. Patnaik, O. Sinanoglu, M. Swaminathan, S. Mukhopadhyay, J. Knechtel, and S. Lim “Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC,” IEEE Transactions on Component, Packaging, and Manufacturing Technology (TCPMT), vol. 10, no. 12, Dec. 2020, pp. 2047-2060.
  7. S. Mukhopadhyay, Y. Long, B. Mudassar, C. Nair,B. H. Deprospo, H. M. Torun, M. Kathaperumal, V. Smet, D. Kim, S. Yalamanchili, and M. Swaminathan, “Heterogenous Integration for Artificial Intelligence: Challenges and Opportunities,” IBM Journal of Research and Development (IBM J. R&D), vol. 63 , no. 6 , Nov.-Dec. 2019, pp. 4.1-4.23.
  8. E. Lee, A. Singh, H. M. Torun, J. Kim, S. K. Lim, M. Swaminathan, and S. Mukhopadhyay, “Automated I/O Library Generation for Interposer-based System-in-Package Integration of Multiple Heterogeneous Dies,” IEEE Transactions on Component, Packaging, and Manufacturing Technology (TCPMT), vol 10, no. 1, Nov. 2019, pp. 111-122.

Conference Articles

  1. J. Kim, V. Chekuri, N. M. Rahman, M. A. Dolatsara, H. Torun, M. Swaminathan, S. Mukhopadhyay, and S. Lim, “Silicon vs. Organic Interposer: PPA and Reliability Tradeoffs in Heterogeneous 2.5D Chiplet Integration,” IEEE International Conference on Computer Design (ICCD), October 2020.
  2. J. Kim, H. Park, E. Lee, D. Kim, A. Chaudhuriy, S. Banerjee, M. Nelson, S. Mukhopadhyay, K. Chakrabarty, and S. K. Lim, “RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory,” GOMACTECH, March 2020.
  3. H. Park, K. Chang, B. W. Ku, J. Kim, E. Lee, D. Kim, A. Chaudhuri, S. Banerjee, S. Mukhopadhyay, K. Chakrabarty, and S. K. Lim, “RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs,” Design Automation Conference (DAC), June 2019.
  4. J. Kim, G. Murali, H. Park, E. Qin, H. Kwon, V. Chekuri, N. Dasari, A. Singh, M. Lee, H. M. Torun, K. Roy, M. Swaminathan, S. Mukhopadhyay, T. Krishna, and S. Kyu Lim, “Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets”, Design Automation Conference (DAC), June 2019.
  5. H. M. Torun, H. Yu, Dasari, V. Chekuri, A. Singh, J. Kim, S. K. Lim, S. Mukhopadhyay, and M. Swaminathan, “A Spectral Convolutional Net for Co-Optimization of Integrated Voltage Regulators and Embedded Inductors,” International Conference on Computer Aided Design (ICCAD), November 2019.
  6. E. Lee, D. Kim, V. Chekuri, Y. Long, and S. Mukhopadhyay, “A ReRAM Memory Compiler with Layout-Precise Performance Evaluation,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018
  7. M. Lee, A. Singh, H. Torun, J. Kim, S Lim, M. Swaminathan, and S. Mukhopadhyay. “ Automated Generation of All-Digital I/O Library Cells for Multiple Dies in System-in-Package Integration,” GOMACTECH, March 2019.
  8. H. M. Torun, N. Dasari, A. Singh, M. Lee,J. Kim, H. Park, H. Kwon, E. Qin, T. Krishna, S. K. Lim, S. Mukhopadhyay and M. Swaminathan, “Design Space Exploration of Power Delivery in Heterogeneous Integration,” GOMACTECH, March 2019.
  9. M. Lee, J. Kim, A. Singh, H. M. Torun, M. Swaminathan, S. Lim, and S. Mukhopadhyay, “On the Design of Energy-Efficient I/O Circuits for Interposer-based 2.5D System-in-Package,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
  10. M. Lee, A. Singh, H. M. Torun, J. Kim, S. Lim, M. Swaminathan, and S. Mukhopadhyay, “Automated Generation of All-Digital I/O Library Cells for System-in-Package Integration of Multiple Dies,” IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2018.