Publications in 2014

Journal Articles

  1. S. Paul, S. Mukhopadhyay, S. Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing,” IEEE Transactions on VLSI (TVLSI), vol. 22, no. 12, Nov. 2014, pp. 2449-2461.
  2. A. Trivedi, S. Datta, and S. Mukhopadhyay, “Application of Silicon-Germanium Source Tunnel-FET to enable Ultra-low power Cellular Neural Network based Associative Memory,” IEEE Transactions on Electron Devices (TED), vol. 61, no. 11, Nov. 2014, pp. 3707-3715.
  3. D. H. Kim, S. Mukhopadhyay, and S. Lim, “TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3D Stacked ICs,” IEEE Transactions on Computer Aided Design, vol. 33, no. 9, Sept. 2014, pp. 1384-1395.
  4. B. Alexandrov, O. Sullivan, W. Song, S. Yalamanchili, S. Kumar, and S. Mukhopadhyay, “Control Principles and On-chip Circuits for Active Cooling using Integrated Super Lattice Based Thin-Film Thermoelectric Devices,” IEEE Transactions on VLSI Systems (TVLSI), vol. 22, no. 9, September 2014, pp. 1909-1919.
  5. K. Z. Ahmed, and S. Mukhopadhyay, “A wide conversion ratio, extended input 3.5µA Boost Regulator with 82% Efficiency for Low Voltage Energy Harvesting,” IEEE Transactions on Power Electronics, vol.29, no.9, Sept. 2014, pp. 4776-4786.
  6. A. Trivedi and S. Mukhopadhyay, “Potential of Ultra-low-power Image Proecssing with Si/Ge Tunneling Nanowires based Cellular Neural Network,” IEEE Transactions on Nanotechnology, vol. 13, no. 4, July 2014, pp. 627-629. The top most accessed article in TNANO in every month from August, 2014 to February, 2015.
  7. A. Trivedi and S. Mukhopadhyay, “In-situ Power Gating Efficiency Learner for Fine-Grain Self Adaptive Power Gating,” IEEE Transactions on Circuits and Systems – II (TCAS-II), vol.61, no.5, May 2014, pp. 344 – 348.
  8. A. Trivedi, T. Ando, A. Singhee, P. Kerber, E. Acar, D. J. Frank, and S. Mukhopadhyay, A Simulation Study of Oxygen Vacancy induced Variability in HfO2/Metal Gated SOI FinFET,” IEEE Transactions on Electron Devices (TED), vol.61, no.5, May 2014, pp.1262-1269.
  9. K. Chae, and S. Mukhopadhyay, “Resilient Pipeline under Supply Noise with Programmable-Time-Borrowing and Delayed-Clock-Gating,” IEEE Transactions on Circuits and Systems – II (TCAS-II), vol.61, no.3, pp.173-177, March 2014.
  10. D. Lie, K. Chae, and S. Mukhopadhyay, “Analysis of the Performance, Power, and Noise Characteristics of a CMOS Image Sensor with 3D Integrated Image Compression Unit,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 4, no.2, Feb. 2014, pp.198-208.
  11. K. Chae and S. Mukhopadhyay, “A Dynamic Timing Error Prevention Technique with Time Borrowing and Clock Stretching to Widen Operating Range of Pipelines,” IEEE Transactions of Circuits and Systems (TCAS-I), vol.61, no.1, Jan. 2014, pp.74-83.
  12. M. Cho, K. Z. Ahmed, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Post-Silicon Characterization and On-Line Prediction of Transient Thermal Field in Integrated Circuits Using Thermal System Identification,” IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol.4, no.1, Jan. 2014, pp.37-45.

Conference Papers (Peer Reviewed)

  1. M. F. Amir, A. Trivedi, and S. Mukhopadhyay, “A Tunnel-FET SRAM Array for Energy-Efficient Embedded Memory Blocks in Reconfigurable computing Platforms,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2014.
  2. Z. Wan, W. Yueh, Y. Joshi, and S. Mukhopadhyay, “On-Chip Temperature and Leakage Power Measurement and Comparison between Air Cooling and Microfluidic Cooling,” THERMINIC Sept. 2014
  3. M. Kar, D. Lie, M. Wolf, V. De, and S. Mukhopadhyay, “Impact of Inductive Integrated Voltage Regulator on the Power Attack Vulnerability of Encryption Engines: A Simulation Study,” IEEE Custom Integrated Circuit Conference (CICC), Sept. 2014.
  4. B. Alexandrov, K. Z. Ahmed, and S. Mukhopadhyay, “An On-Chip Autonomous Thermoelectric Energy Management System for Energy-Efficient Active Cooling,” IEEE International Symposium on Low-power Electronic Design (ISLPED), Aug. 2014. Best Paper Award.
  5. M. Kar, S. Carlo, H. Krishnamurthy, and S. Mukhopadhyay, “Impact of the Process Variation in Inductive Integrated Voltage Regulator on Delay and Power of Digital Circuits,” IEEE International Symposium on Low-power Electronic Design (ISLPED), Aug. 2014.
  6. D. Kim and S. Mukhopadhyay, “On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking,” IEEE/ACM Design Automation Conference (DAC), June 2014.
  7. A. Trivedi, M. F. Amir, and S. Mukhopadhyay, “Ultra-low Power Electronics with Si/Ge Tunnel FET,” Design, Automation, and Test in Europe (DATE), March 2014.
  8. A. Trivedi and S. Mukhopadhyay, “Si/Ge Tunneling Nanowires based Low Power Cellular Neural Network,” GOMACTech March 2014
  9. W. Yueh, K. Z. Ahmed, and S. Mukhopadhyay, “Field Programmable Thermal Emulator (FPTE): An All-Silicon Test Structure for Thermal Characterization of Integrated Circuits,” IEEE Semi Therm March 2014. Honorable Mention in the Best Paper Award Selection.
  10. S. Parthasarathy, K. Z. Ahmed, B. Alexandrov, S. Kumar, and S. Mukhopadhyay, “Energy Efficient Active Cooling of Integrated Circuits Using Autonomous Peltier/Seebeck Mode Switching of a Thermoelectric Module,” IEEE Semi Therm, March 2014.