Publications in 2017

Journals

  1. A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Reducing Side-Channel Leakage of Encryption Engines Using Integrated Low-Dropout Voltage Regulators,” Journal of Hardware and Systems Security, vol.1, December, 2017, pp. 340-355.
  2. W. Yueh, Z. Wan, H. Xiao, S. Yalamanchili, Y. Joshi and S. Mukhopadhyay, “Active Fluidic Cooling on Energy Constrained System-on-Chip Systems,” in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 11, pp. 1813-1822, Nov. 2017.
  3. J. H. Ko, K. Z. Ahmed, M. F. Amir, T. Na, and S. Mukhopadhyay, “A Single-Chip Image Sensor Node with Energy Harvesting from CMOS Pixel Array” J. H. Ko, M. F. Amir, K. Z. Ahmed, T. Na and S. Mukhopadhyay, “ IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, Sept. 2017, pp. 2295-2307.
  4. T. Na, J. H. Ko, and S. Mukhopadhyay, “Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, Sept. 2017, pp. 2401-2413.
  5. M. Kar, A. Singh, A. Rajan, V. De, and S. Mukhopadhyay, “An All-Digital Fully Integrated Inductive Buck Regulator with A 250MHz Multisampled Compensator and A Lightweight Auto-Tuner in 130nm CMOS,” IEEE Journal of Solid State Circuits (JSSC), vol. 52, no. 7, July 2017, pp. 1825 – 1835.
  6. D. Kim, J. H. Kung, and S. Mukhopadhyay, “A Power-Aware Digital Multilayer Perceptron Accelerator with On-Chip Training based on Approximate Computing,” IEEE Transactions on Emerging Topics in Computing (IEEE TETC), vol. 5, no. 2, April-June 2017, pp. 164-178.

Conference Papers (Peer Reviewed)

  1. T. Na, J. H. Ko, and S. Mukhopadhyay, “Cascade Adversarial Machine Learning  Regularized with a Unified Embedding,” Machine Learning and Computer Security Workshop, Neural Information Processing Systems (NIPS), 2017.
  2. A. Singh, M. Kar, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power Side Channel Attack Resistance of a 128-Bit AES Engine with Random Fast Voltage Dithering,” IEEE European Solid State Circuit Conference (ESSCIRC), 2017.
  3. J. H. Ko, Y. Long, M. F. Amir, D. Kim, J. Kung, T. Na, A. Trivedi, and S. Mukhopadhyay, “Energy-Efficient Neural Image Processing for Internet-of-Things Edge Devices,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Aug. 2017.
  4. (Invited) M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Low Power Requirements and Side-Channel Protection of Encryption Engines: Challenges and Opportunities,” International Symposium on Low-power Electronics and Design, ISLPED 2017.
  5. J. Kung, Y. Long, D. Kim, and S. Mukhopadhyay, “A Programmable Hardware Accelerator for Simulating Dynamical Systems,” IEEE International Symposium on Computer Architecture (ISCA), 2017.
  6. J. H. Ko, T. Na, and S. Mukhopadhyay, “Design of An Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation,” Design Automation Conference (DAC), 2017.
  7. T. Na, J. H. Ko, J. Kung, and S. Mukhopadhyay, “On-Chip Training of Recurrent Neural Networks with Limited Numerical Precision,” accepted for presentation at International Joint Conference on Neural Network (IJCNN), May 2017.
  8. J. H. Ko, and S. Mukhopadhyay, “A Low-Power Wireless Image Sensor Node with Noise-Robust Moving Object Detection and a Region-of-Interest Based Rate Controller,” Accepted for presentation at 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2017.
  9. J. Kung, Y. Long, D. Kim, and S. Mukhopadhyay, “An Energy-Efficient Physical Platform for Solving Differential Equations,” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2017.
  10. A. Trivedi, and S. Mukhoapdhyay, “CMOS-based Stochastically Spiking Neural Network for Optimization under Uncertainties,” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech), 2017.
  11. J. H. Ko, D. Kim, T. Na, J. Kung, and S. Mukhopadhyay, “Adaptive Weight Compression for Memory-Efficient Neural Networks,” Design, Automation, and Test in Europe (DATE), 2017.
  12. T. Na, J. H. Ko, and S. Mukhopadhyay, “Clock Data Compensation Aware Clock Tree Synthesis in Digital Circuits with Adaptive Clock Generation,” Design, Automation, and Test in Europe (DATE), 2017.
  13. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power Side-Channel Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator,” International Solid State Circuit Conference (ISSCC), 2017.